The present invention relates to an apparatus and method for providing delayed clock edges with new delay values every clock period for use in loading delay data.
Timing on the fly (TOF) solutions have used delay update schemes that feature the following. One feature involves initiating output enable in a system clock domain. This feature allows for simple communication between a core integrated circuit (IC) and a corresponding delay line control section, where new delay data is loaded into delay lines on the xe2x80x9coff-edgexe2x80x9d of the input to the delay lines. Although a workable solution, important processing time is consumed for the xe2x80x9coff edgexe2x80x9d to arrive to allow the new data to be loaded.
In conventional TOF systems, no provisions exist for xe2x80x9cblanking outxe2x80x9d transients caused by reprogramming the delay lines. The use of the restrictive core clock domain control identified above, severely restricts the use of techniques to blank reprogramming transients when delay values are changed every input clock cycle.
TOF systems have also featured using twice the number of delay lines so that one delay line is used every other cycle. This methodology allows one delay line to be operational while the other is being reprogrammed. However, it requires additional delay lines, which increases the TOF complexity and IC chip space.
Accordingly, a need exists for improvements in providing delayed clock edges for use in loading delay data.
A circuit consistent with the present invention provides split fine and coarse delay control of delay lines for use in loading delay data. It includes a fine delay, controlled by a fine delay line, receiving a clock signal and outputting a fine delay signal. A coarse delay, controlled by a coarse delay line, receives the fine delay signal and outputs a coarse delay signal. Gating logic receives the coarse delay signal and outputs a gated delay signal for loading delay data.
A polarity blanking delay circuit consistent with the present invention provides for blanking transients for use in loading delay data. It includes a delay, controlled by a delay line, receiving a clock signal and outputting a first delay signal. A latch, clocked by the first delay signal, receives a particular input signal and outputs a second delay signal. A blanking circuit receives the clock signal and a control signal, and it outputs a blanking signal to a control input of the latch for use in blanking transients in the first delay signal.
A circuit consistent with the present invention provides adjustable blanking of transients for use during loading of delay data. It includes a fine delay receiving a clock signal and outputting a fine delay signal. A coarse delay, controlled by a coarse delay line, receives the fine delay signal and outputs a coarse delay signal. A latch, clocked by the coarse delay signal, receives a particular input signal and outputs a delayed clock signal. A blanking generator receives a control signal and outputs an adjustable blanking signal to a control terminal of the latch for use in blanking transients in the delayed clock signal.